Kandou’s PCI CXL Manager Rommel Camillo recently gave an interview to PCI-SIG, sharing some insights into the ways that chiplets are empowering the next generation of PCIe systems.

Chiplets are nothing new, and we’ve explained in detail their history and benefits here on a previous blog. But as Rommel points out, their value and use are poised to explode with the upcoming leap forward in PCIe. The transition from Gen5 transfer rates of 32GB/s to 64G means that maintaining data and signal integrity, with switches and retimers, is crucial.

Put simply, instead of one monolith semiconductor, bound by bandwidth and power limitations, chiplets fragment duties into more flexible ‘tiles’. A switch or retimer could start with a very simple 4×4 configuration, with the option to scale up to x8 and x16 for other products.

The inherent limitations placed on systems by equipment mean it’s definitely chiplets’ time to shine, especially since they can open doors for heterogenous applications too. Rommel outlines how a quartet of an SOC tile, a compute tile, an IO tile, and a graphics tile can provide opportunities for unique use cases and AI applications.

At present there is no standard interconnect, but Kandou’s Glasswing IP offers the low power and ultra-low bit error rate that the industry needs to start scaling with retimers, especially with AI.

As PCIe moves increasingly beyond the motherboard, smart cabling allows designers to deploy the same speeds and signal integrity board to board – within the same rack – inviting even broader component integration and rack optimisation for data centres and hyperscalers.

To find out more, you can watch Rommel’s PCI-SIG interview in full on YouTube here.